Sep 2021 – Jun 2026
Ph.D., Fudan University Integrated Circuit and System Design.
Research Interests:
- Very Large-Scale Integration (VLSI) Placement Algorithms;
- Physical aware Synthesis Flow ;
- Timing Prediction and Static Timing Analysis.
Ph.D., Fudan University Integrated Circuit and System Design.
Research Interests:
B.S., Fudan University Microelectronic Science and Engineering.
Thesis Title: Timing-Driven Detailed Placement for large-scale heterogeneous FPGAs.
Senior Engineer, Shanghai LEDA Technology Co., Ltd.
Agentic EDA: Building an industrial-grade RTL-to-GDS agent that drives the implementation flow end to end with almost no human intervention, targeting better PPA and lower power.
LLM Infrastructure: Local deployment of large language models, inference-efficiency optimization for coding-agent workloads, and the setup and management of LLM gateways.
Software Development & Product Application Intern, Shanghai LEDA Software Technology
Responsibilities: Participated in the localization substitution and optimization of EDA tools in multiple partitions (e.g., XPU, GPU) on SMIC process nodes. Responsible for building the workflow and optimizing PPA results for the Pre-CTS stage using domestic EDA tools.
Software Development Intern, Shanghai LEDA Software Technology
Responsibilities: Developed a timing prediction tool using placement results to bridge logic synthesis and physical design. This allowed for re-synthesis flow, which optimized the netlist and placement for better performance.
Software Development Intern, Shanghai LEDA Software Technology
Responsibilities: Optimized wirelength and prevented timing violations using analytical placement methods. Developed and integrated custom algorithms into domestic EDA tools, achieving superior PPA results on industrial benchmarks.
Publications: Electrostatics-based analytical global placement for timing optimization [3]; An Analytical Placement Algorithm with Routing topology Optimization [1]
Software Development Intern, Shanghai Fudan Microelectronics Group
Responsibilities: Contributed to the development of EDA tools for FPGA design. Assisted in developing a detailed placement tool for FPGAs, where the related algorithms effectively improved the timing quality of FPGA layouts.
CET-6, proficient in technical document reading and writing, capable of daily communication and academic discussions
C/C++, Python, Tcl, Shell (Bash, CShell), LaTeX, …
Cadence Innovus, Synopsys Design Compiler, Mentor Graphics ModelSim, Cadence Virtuoso, Synopsys VCS, Xilinx Vivado
Verilog, SDC, DEF/LEF, Liberty, SystemVerilog, UVM
Git, (Neo)Vim, CMake, Linux, Docker, Agile Development Workflow
First Place, ISPD 2023 Contest.
Topic: Security Closure of Physical Layouts
Contribution: Built a full chip implementation flow using Cadence Innovus tool, achieving co-optimization of PPA metrics and layout security.
Publications: Layout-level Hardware Trojan Prevention in the Context of Physical Design [2]
First Prize, 4th China Postgraduate IC Innovation Competition.
Third Prize, 3rd EDA Elite Challenge Contest.
Honorable Mention, 2022 CAD Contest @ICCAD.
Second Place, 2023 CAD Contest @ICCAD.
First Prize, 5th EDA Elite Challenge Contest.
China Education Development Foundation Endeavor Scholarship—Integrated Circuit
Third Place, ISPD 2024 Contest.